1. Field of the Invention
The present invention relates to an input buffer for a memory device, and more particularly to an input circuit for a memory device which can improve the data processing speed by controlling the operation of an input multiplexer for determining a transfer path of data having passed through a data input buffer.
2. Description of the Prior Art
The processing speed of a semiconductor memory device becomes faster and faster. In addition, with the development of DDR SDRAM that can access two data with one clock, the processing speed of the memory device becomes much faster. The process of input data of the memory device is one of important issues in improving the processing speed of the memory device.
FIG. 1 illustrates a conventional data input circuit of a memory device. For reference, the memory device mentioned in the description refers to a DDR SDRAM and a DDR2 SDRAM that is the next-generation memory device.
As shown in FIG. 1, the conventional data input circuit of a memory device includes data buffers 101 and 102, an input multiplexer 103, data bus writers 105 and 106, block writers 107 and 108, and an input selection signal generating unit 194 for controlling the operation of the data bus writers 105 and 106.
For convenience in explanation, FIG. 1 illustrates only two data buffers 101 and 102, but the number of data buffers is 16 if the data input/output structure of the memory device is X16. Accordingly, it can be recognized that 14 buffers further exist in addition to the two data buffers 101 and 102 illustrated in FIG. 1.
The basic operation of the conventional data input circuit will now be explained.
The data buffers 101 and 102 controlled by a control signal Din clk receives corresponding data D0 and D1 and output data D0_1 and D1_1. Here, the control signal Din clk is a signal (or a clock) generated as many as BL/2 times, and indicates a signal generated in synchronization with a rising edge of the first data strobe signal (hereinafter referred to as a “DQS signal”).
The input multiplexer 103 is a constituent element that determines transfer paths of the data D0_1 and D1_1. Here, the reason why the transfer paths of the data are determined is that the memory device having a data input/output structure of X16 may use a data input/output structure of X8 as needed.
For example, it is assumed that if the data pins of the memory device are set to X16, 16-bit data is applied. In this case, the data D0_1 is transferred to the data bus writer 105 along a solid line as indicated in FIG. 1, and the data D1_1 is transferred to the data bus writer 106 along a solid line as indicated in FIG. 1. The remaining data D2_1, . . . , D15_1 are transferred in the same manner.
Also, it is assumed that 8-bit data is applied in a state that the data pins of the memory device are set to X16. In this case, the remaining 8 buffers except for the 8 buffers being used become unnecessary.
Meanwhile, it should be determined which data bus writer between the two data bus writers 105 and 106 the data having passed through the data buffers 101 and 102 is transferred to by the input multiplexer 103. For example, the data D0_1 having passed through the data buffer 101 is transferred to one of the two data bus writers 105 and 106 by the input multiplexer 103. The input multiplexer 103 serves to determine the data transfer path if the data composed of bits smaller than the prescribed bits is applied.
The data bus writers 105 and 106 transfer the data from the input multiplexer 103 to a global input lines gio0 and gio1. In the case that the memory device having the data input/output structure of X16 operates, the data bus writers transfer the data from the input multiplexer to the global input/output lines as they are. By contrast, in the case that the memory device having the data input/output structure of X8 operates, the output terminals of the data bus writer to which no data is inputted are kept in an initial state or in a pre-charge state.
The block writers 107 and 108 transfer the data to a memory block (not illustrated) through local input lines lio0 and lio1. Here, the memory block means a partitioned area in a memory bank (i.e., a memory bank is composed of a plurality of memory blocks).
The input selection signal generating unit 104 receives a 2-clock-shifted block column address and a control signal clk Din and outputs a signal for controlling the operation of the data bus writers 105 and 106. Here, the 2-clock-shifted block column address, as shown in FIG. 2, is a signal that is 2-clock-delayed in comparison to a column address inputted by a write command, and is for selecting a specified block of the memory bank. The control signal clk Din is a clock signal generated as many as BL/2 times after being 2-clock-delayed after the write command. That is, as shown in FIG. 2, the control signal clk Din is a clock signal generated in synchronization with the rising edge of the clock at a time point t3.
FIG. 2 is a waveform diagram illustrating waveforms appearing at various point of the circuit of FIG. 1.
In FIG. 2, the term “clk” denotes a clock signal applied to the memory device and the control signal Din clk is a signal for controlling the data buffers 101 and 102. The data D0_2 indicates data outputted from the input multiplexer 103. The control signal clk Din is a clock signal generated after being 2-clock-delayed after the write command. The 2-clock-shifted block column address is 2-clock-delayed in comparison to the column address inputted in synchronization with the same clock as the write command input.
In operation, the input selection signal generating unit 104 enables the data bus writers 105 and 106 if both the 2-clock-shifted block column address and the control signal clk Din are in a high level.
However, according to the conventional data input circuit, the control signal is generated when a predetermined time elapses after the 2-clock-shifted block column address is generated, and this causes the driving time of the data bus writers to be delayed as much as the predetermined time. This finally causes the data transfer speed to deteriorate.